Recently, it is difficult to miniaturize a nonvolatile semiconductor memory using a conventional floating gate, so that a resistance-change memory including a three-dimensional crosspoint cell is expected as a candidate for a further high-capacity memory. Among other resistance-change memories, a resistive random access memory (ReRAM) using a variable-resistance element is a leading next-generation nonvolatile semiconductor memory. Meanwhile, resolution is difficult with conventional exposure technology when forming a recent memory device, so that double patterning technology using a sidewall spacer is generally used.
The crosspoint cell of the ReRAM includes the variable-resistance element and a diode between interconnects (word line and bit line) orthogonal to each other and they are arranged in a matrix pattern and in a three-dimensional array pattern on upper and lower layers. When applying a voltage to the variable-resistance element, this transits to a low-resistance state in which resistance decreases at a certain voltage (Vset). This is referred to as set (writing). Also, when applying the voltage to the variable-resistance element in the low-resistance state and applying current, this transits to a high-resistance state at a certain voltage (Vreset). This is referred to as reset (erasing). By detecting the low-resistance state or the high-resistance state as a difference in flowing current, binary 0 or 1 stored in the memory cell is detected.
When manufacturing the three-dimensional crosspoint cell using the double patterning technology, there is the following problem.
Since the number of extraction sections is proportional to “number of interconnect laminations×number of divisions of cell array” in the ReRAM, even when increase in an area is a few microns for each portion, the total area increases exponentially and miniaturization becomes difficult.